1. Field of the Invention
The present invention generally relates to semiconductor memory devices and a method of setting a test mode, and more particularly, to a semiconductor memory device having a test mode which is set based on an external control signal and a method of setting the test mode.
2. Description of the Background Art
With a semiconductor memory device made large in memory capacity in recent years, a function test of a memory cell array in the semiconductor memory device after manufacture has become more important. However, a time required for such a function test becomes longer as the number of memory cells included in the memory cell array increases, that is, the memory capacity of the semiconductor memory device increases. Therefore, increase of a time required for such a function test in the semiconductor memory device with large memory capacity has become a problem in recent years.
In order to shorten a time required for such a function test, a so-called on-chip test circuit system is employed recently in many cases in which a circuit unit for such a function test (hereinafter referred to as a "test circuit") is provided on the same chip together with circuits constituting a semiconductor memory device. For example, such an on-chip test circuit system is used in a DRAM (Dynamic Random Access Memory) in many cases.
FIG. 7 is a block diagram showing the entire configuration of a DRAM in which the on-chip test circuit system is employed. Referring to FIG. 7, a memory cell array 1 includes memory cells (not shown) arranged in rows and columns in a matrix manner, word lines (not shown) provided one for each row, and bit line pairs (not shown) provided one pair for each column. Each of the memory cells is connected to a word line of a corresponding row and a bit line pair of a corresponding column.
Selection of any word line is carried out by a row decoder 2, and selection of any bit line pair is carried out by a column decoder 3. Word line selection by row decoder 2 and bit line pair selection by column decoder 3 are carried out in response to a row address signal RA0 to RA9 and a column address signal CA0 to CA9 provided from an address buffer 4, respectively.
Address buffer 4 incorporate either an internal address signal Q0 to Q9 provided from a refresh counter 8 or an external address signal A0 to A10, based on an internal row address strobe signal intRAS provided from a RAS input circuit 10 and an internal column address strobe signal intCAS provided from a CAS input circuit 12.
Furthermore, address buffer 4 provides the row address signal RA0 to RA10 and the column address signal. CA0 to CA10 corresponding to the incorporated address signal. In the normal data reading operation and the normal data writing operation, address buffer 4 incorporates the external address signal A0 to A10. In the refresh operation in which data is rewritten in the memory cells before memory data of the memory cells in memory cell array 1 disappears, address buffer 4 incorporates the internal address signal Q0 to Q9 from refresh counter 8.
A refresh controller 9 instructs output of the internal address signal to refresh counter 8 at a predetermined timing, based on the internal row address strobe signal intRAS from RAS input circuit 10. Refresh counter 8 generates the internal address signal Q0 to Q9 indicating the address of the memory cell having memory data to be refreshed, in response to instruction from refresh controller 9.
Row decoder 2 carries out word line selection based on the row address signal RA0 to RA9 from address buffer 4 at a timing based on the internal row address strobe signal intRAS from RAS input circuit 10. On the other hand, column decoder 3 carries out bit line pair selection based on the column address signal CA0 to CA9 from address buffer 4 at a timing based on the internal column address strobe signal intCAS from CAS input circuit 12.
More specifically, column decoder 3 controls an I/0 gate 5 in order to electrically connect only a bit line pair corresponding to the column address signal CA0 to CA10 out of bit line pairs in memory cell array 1 to an input buffer 6 or an output buffer 7 at a timing corresponding to the internal column address strobe signal intCAS.
I/O gate 5 includes transfer gates (not shown) provided corresponding to respective bit line pairs in order to connect bit line pairs in memory cell array 1 to input buffer 6 and output buffer 7. Column decoder 3 carries out bit line pair selection by bringing into an on state only a transfer gate corresponding to a bit line pair of a column address indicated by the column address signal CA0 to CA9 out of the transfer gates included in I/O gate 5.
A sense amplifier 15 amplifies data (read out data) which appears in each of the bit line pairs in memory cell array 1 in the data reading operation. By bit line pair selection operation of column decoder 3, only a bit line pair corresponding to the address signal out of the bit line pairs in memory cell array 1 is connected to output buffer 7 through I/O gate 5. Therefore, only read out data which appears in the corresponding bit line pair out of the bit line pairs in memory cell array 1 is applied to a data output terminal D.sub.out through output buffer 7 after being amplified by sense amplifier 15.
In the data writing operation, data applied to a data input terminal D.sub.in is applied to I/O gate 5 through input buffer 6. As a result, externally applied data is written in a selected memory cell through a bit line pair selected by column decoder 3 out of the bit line pairs in memory cell array 1.
Reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 8-bit basis in maximum. However, in the normal data writing operation and the normal data reading operation, an I/O controller 11 controls input buffer 6 and output buffer 7 so that reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 4-bit basis.
I/O controller 11 controls input buffer 6 and output buffer 7, based on the least significant bits RA10 and CA10 in the row address signal RA0 to RA0 and the column address signal CA0 to CA10, respectively, provided from address buffer 4 and the internal write enable signal intWE provided from WE input circuit 13.
More specifically, in the data reading operation in which the internal write enable signal intWE is at a logic high or "H" level, I/O controller 11 controls operation of output buffer 7 based on the row address signal bit RA10 and the column address signal bit CA10 so that output buffer 7 provides only 1-bit data corresponding to the address designated by the row address signal bit RA0 and the column address signal bit CA10 out of 4-bit data incorporated from I/O gate 5.
Similarly, in the data writing operation in which the internal write enable signal intWE is at a logic low or "L" level, I/O controller 11 controls operation of input buffer 6 based on the row address signal bit RA10 and the column address signal bit CA10 so that input buffer 6 incorporates data applied from the data input terminal D.sub.in to apply the same to a transfer gate corresponding to a bit line pair of the address designated by the row address signal bit RA10 and the column address signal bit CA10 out of the transfer gates in I/O gate 5.
In the refresh operation, data read out to output buffer 7 is again applied to I/O gate 5 as writing data. Since address buffer 4 incorporates the internal address signal Q0 to Q9 from refresh counter 8 in the refresh operation, memory data of the memory cell of the address instructed by the internal address signal Q0 to Q9 is refreshed.
In a test mode in which a function test of memory cells in memory cell array 1 is carried out, reception and transmission of data among I/O gate 5, input buffer 6 and output buffer 7 are carried out on the 8-bit basis. More specifically, in the test mode, column decoder 3, input buffer 6 and output buffer 7 operate in response to a test enable signal TE of an "L" level from a test mode controller 14.
When described more specifically, column decoder 3 ignores the least significant bit CA10 of the column address signal, and decodes only the higher bits CA0 to CA9 of the column address signal to carry out bit line selection, during a period when it receives the test enable signal TE of an "L" level from test mode controller 14. As a result, the number of bit line pairs selected by column decoder 3 at one time is made double of that in the normal data reading operation and the normal data writing operation.
On the other hand, during a period when input buffer 6 receives the test enable signal TE of an "L" level from test mode controller 14, it is controlled by I/O controller 11 to apply 8-bit data provided at the data input terminal D.sub.in to I/O gate 5 in parallel.
Similarly, during a period when output buffer 7 receives the test enable signal TE of an "L" level from test mode controller 14, output buffer 7, controlled by I/O controller 11, detects match and mismatch of the 8-bit data applied from I/O gate 5 in parallel with written data to provide the result to the data output terminal D.sub.out.
Therefore, the result of determination of whether or not all the data read out to eight pairs of bit line pairs selected by column decoder 3 in the test mode matches the written data is provided outside through output buffer 7. The externally applied 8-bit writing data is applied to the eight pairs of bit line pairs in parallel through input buffer 6.
A function test of a memory cell array is carried out by, after writing a predetermined data in all or a part of the memory cells included in the memory cell array, reading out data from the memory cell in which the data is written, to determine whether or not the read out data matches the data written in advance. Therefore, by the above-described operation of column decoder 3, input buffer 6 and output buffer 7 in the test mode, tests for eight memory cells are automatically carried out simultaneously. More specifically, in the test mode, the memory cells in memory cell array 1 are tested automatically for every eight memory cells. It should be noted that a pattern and the like of the data written in the memory cell array for testing depend on the kind of the test.
Test mode controller 14 is a circuit for setting the DRAM in the test mode based on the internal row address strobe signal intRAS from RAS input circuit 10, the internal column address strobe signal intCAS from CAS input circuit 12, and the internal write enable signal intWE from WE input circuit 13.
RAS input circuit 10, CAS input circuit 12, and WE input circuit 13 buffer the external row address strobe signal RAS, the external column address strobe signal CAS, and the external write enable signal WE which are external control signals, to provide the buffered signals as the internal row address strobe signal intRAS, the internal column address strobe signal intCAS, and the internal write enable signal intWE, respectively. Therefore, the internal control signals intRAS, intCAS, and intWE have waveforms substantially the same as those of the external control signals RAS, CAS, and WE, respectively.
Description will now be given on specific operation of test mode controller 14 with reference to FIG. 8. FIG. 8 is a waveform diagram showing waveforms of the external row address strobe signal RAS (a), the internal row address strobe signal intRAS (b), the external column address strobe signal CAS (c), the internal column address strobe signal intCAS (d), the external write enable signal WE (e), the internal write enable signal intWE (f) and the test enable signal TE (g), when test mode controller 14 sets the DRAM in the test mode.
Referring to FIG. 8, test mode controller 14 is activated when the internal signals intCAS (FIG. 8 (d)) and intWE (FIG. 8 (f)) both are already at an "L" level at a time t1 of the fall of the internal signal intRAS (FIG. 8 (b)). Activated test mode controller 14 causes the test enable signal TE (FIG. 8 (g)) to fall to an "L" level. As a result, column decoder 3, input buffer 6 and output buffer 7 in FIG. 5 carry out operation for a test as described above.
Since test mode controller 14 operates as described above, a user may set timings of respective signals so as to cause the external control signal RAS to fall to an "L" level during a period when the external control signals CAS and WE both are at an "L" level, in order to set the DRAM in the test mode. A method of setting a test mode is determined internationally by Joint Electron Device Engineering Council (JEDEC).
Referring again to FIG. 7, a power-on-reset circuit 16 receives a voltage V.sub.CC supplied from an external power source (not shown). Power-on-reset circuit 16 applies a one-shot pulse of an "H" level to predetermined circuit units in the DRAM in response to the rise of the power supply voltage V.sub.CC, that is, power-on to the DRAM. The one-shot pulse is called a power-on-reset signal POR.
Potentials of predetermined nodes in the predetermined circuit units are forced to respective levels to be taken in the initial state by the power-on-reset signal POR. As a result, the predetermined circuit units are brought into reset states at the initiation of operation. The power-on-reset signal POR is applied to, for example, RAS input circuit 10 as well as test mode controller 14. As described above, a semiconductor memory device generating a reset signal at the time of power-on is disclosed in, for example, Japanese Patent Laying-Open No. 2-29118 and Japanese Patent Laying-Open No. 63-98213.
Although it is shown in FIG. 7 that the output POR of power-on-reset circuit 16 is applied only to RAS input circuit 10 and test mode controller 14, the output POR is actually applied to the other circuit units as necessary.
In response to the applied power-on-reset signal POR, test mode controller 14 forcibly maintains the test enable signal TE at an "H" level during a period when the power-on-reset signal POR is at an "H" level, and retains the reset state so that the DRAM will not enter the test mode.
FIGS. 9 and 10 are waveform diagrams showing reset operation of the test mode controller by the above-described power-on-reset signal POR. FIG. 9 shows operation in the state where the external row address strobe signal RAS (c), the external column address strobe signal CAS (e), and the external write enable signal WE (g) all are already at an "H" level at the time of power-on (time t.sub.2) to the DRAM.
In the case of FIG. 9, as the power supply voltage V.sub.CC (a) rises after power-on at the time t.sub.2, the power-on-reset signal POR (b), the internal row address strobe signal intRAS (d), the internal column address strobe signal intCAS (f), the internal write enable signal intWE (h) and the test enable signal TE (i) rise to an "H" level simultaneously to reach the respective initial states. As described above, the power-on-reset signal POR maintains an "H" level during a predetermined reset period since its rise, and falls to an "L" level at a time t.sub.3.
The power-on-reset signal POR is supplied to each unit in the DRAM such as RAS input circuit 10 and test mode controller 14 as shown in FIG. 7. Therefore, during the reset period, signals in respective units in the DRAM shown in FIG. 9 maintain the respective initial states. Especially when focusing on the test mode, the test enable signal TE is maintained at an "H" level during a reset period as shown in FIG. 9 (i), and the DRAM is prevented from entering the test mode during this period.
On the other hand, FIG. 10 shows operation in the state where the external row address strobe signal RAS, the external column address strobe signal CAS, and the external write enable signal WE rise simultaneously after power-on to the DRAM and after a lapse of the above-mentioned reset period. In the case of FIG. 10, the above-described three external control signals slowly rise from a certain time after the time t.sub.3 to attain an "H" level. Accordingly, corresponding three internal control signals, that is, the internal row address strobe signal intRAS, the internal column address strobe signal intCAS, and the internal write enable signal intWE respectively rise to an "H" level rapidly at the timings when the corresponding external control signals attain respective threshold levels for recognizing as an "H" level.
The test enable signal TE is initialized to an "H" level during the reset period, thereby preventing the DRAM from entering the test mode during the reset period.
In the operation shown in FIG. 10, there is a case where the rises of the three internal control signals sometimes occur at the timings slightly different from one another as described above. For example, as shown in FIG. 10, there may be a case where the internal row address strobe signal intRAS rapidly rises at a time t.sub.4, while the internal column address strobe signal intCAS and the internal write enable signal WE rise rapidly at a time t.sub.5 with a little delay. In such a case, between the times t.sub.4 and t.sub.5, the internal row address strobe signal intRAS accidentally attains an "H" level, and the internal column address strobe signal intCAS and the internal write enable signal intWE accidentally attain an "L" level. Test mode controller 14 results in erroneous recognition that the precondition for setting of the test mode by the above-described JEDEC standard are satisfied.
Therefore, in such a case, if the internal row address strobe signal intRAS temporarily falls from an "H" level to an "L" level (a portion shown by a broken line of FIG. 10 (d) and FIG. 11)) by variation caused by a noise or the like in the vicinity of a threshold value of, for example, the external row address strobe signal RAS, test mode controller 14 erroneously generates the test enable signal TE designating the test mode accordingly (a portion shown by a broken line of FIG. 10 (i)). As a result, contrary to the user's intention, the DRAM unnecessarily enters the test mode right after power-on, causing malfunction of the DRAM.